T
Tomas Whitlock
Guest
Hi all,
I\'m working on a tool that is supposed to read VHDL and create an abstract representation of a design unit.
I have run into a problem where I\'m trying to understand how this common form of an entity declaration + architecture body is accepted by VHDL compilers such as Vivado Simulator / Synthesis, ModelSim / Questa and no doubt others:
entity e is
...
end entity;
architecture a of e is
...
begin
...
end architecture;
After repeatedly reading the VHDL LRMs of \'93, 2002, 2008 etc., it seems to me that, if the rules are interpreted literally, the entity \'e\' should not be visible to at the point where the architecture body declaration references it.
Yet all of the VHDL compilers that I\'ve ever encountered will happily accept the above VHDL as valid.
The LRM mentions a \"library declarative region\", in which primary design units of that library are visible, but it doesn\'t say where it applies. The LRM doesn\'t seem to leave much room for the library declarative region to be nested within some other declarative region, so I don\'t know what to make of it.
So my question is:
Do most VHDL compilers bend the rules and add some additional rules of their own (for example, adding \"use work.all;\" to the predefined language environment), or am I missing something in the LRM that makes the entities of the work library visible to an architecture body declaration (when being compiled into the same work library)?
Thanks in advance for any insights.
I\'m working on a tool that is supposed to read VHDL and create an abstract representation of a design unit.
I have run into a problem where I\'m trying to understand how this common form of an entity declaration + architecture body is accepted by VHDL compilers such as Vivado Simulator / Synthesis, ModelSim / Questa and no doubt others:
entity e is
...
end entity;
architecture a of e is
...
begin
...
end architecture;
After repeatedly reading the VHDL LRMs of \'93, 2002, 2008 etc., it seems to me that, if the rules are interpreted literally, the entity \'e\' should not be visible to at the point where the architecture body declaration references it.
Yet all of the VHDL compilers that I\'ve ever encountered will happily accept the above VHDL as valid.
The LRM mentions a \"library declarative region\", in which primary design units of that library are visible, but it doesn\'t say where it applies. The LRM doesn\'t seem to leave much room for the library declarative region to be nested within some other declarative region, so I don\'t know what to make of it.
So my question is:
Do most VHDL compilers bend the rules and add some additional rules of their own (for example, adding \"use work.all;\" to the predefined language environment), or am I missing something in the LRM that makes the entities of the work library visible to an architecture body declaration (when being compiled into the same work library)?
Thanks in advance for any insights.