hvordan man løser denne fejl?

[cloudz88]

# Loading work.ram0 (ram0_a)
# ** Error: (vsim-3732) assignment2a.vhd (7

<img src="http://www.edaboard.com/images/smiles/icon_cool.gif" alt="Kølig" border="0" />

: Ingen standard bindende for komponent 'U2'.
# (Port 'dout' er ikke på enhed.)
# Region: / testbench/u1/u2
# Loading C: \ Modeltech_xe_starter \ win32xoem/../xilinx/vhdl/xilinxcorelib.blkmemdp_v6_3 (behavioral)
# Error loading design-------------------------------------------------- ------------------------------------------

min kode

enhed assignment2a er

Port (Trigger: i std_logic;
Reset: i std_logic;
X: i std_logic_vector (9 downto 0);
Romrdy: out std_logic;
output: out std_logic_vector (9 downto 0);
n_clk: i std_logic;
m_clk: i std_logic
);

ende assignment2a;

architecture Behavioral af assignment2a erSignal Counter: std_logic_vector (3 downto 0);
Signal AddrA: std_logic_vector (9 downto 0);
Signal Dina: std_logic_vector (9 downto 0);
Signal WEA: std_logic;
Signal ENA: std_logic;
Signal AddrB: std_logic_vector (9 downto 0);
Signal Dout: std_logic_vector (9 downto 0);

Komponent ram0 er
port (
AddrA: InOut std_logic_vector (9 downto 0);
Dina: i std_logic_vector (9 downto 0);
WEA: i STD_LOGIC;
ENA: i STD_LOGIC;
ClkA: i STD_LOGIC;
AddrB: InOut std_logic_vector (9 downto 0);
Dout: out std_logic_vector (9 downto 0);
ClkB: i STD_LOGIC
);

ende Komponent;

begynd

U2: komponent Ram0 Port Map (AddrA => AddrA,
AddrB => AddrB,
Dina => Dina,
WEA => WEA,
ENA => ENA,
ClkA => m_clk,
Dout => Dout,
ClkB => n_clk
);

 

[shockie]

Jeg er ikke sikker på, hvis du har for at kontrollere disse kode:

"U2: komponent Ram0 Port Map (AddrA => AddrA,"
AddrB => AddrB,
Dina => Dina,
WEA => WEA,
ENA => ENA,
ClkA => m_clk,
Dout => Dout,
ClkB => n_clk
);

 

[ship_baba]

hej

tjekke din kildefil til dout