kunne du hjælpe mig om dette vhdl fejl

[minemercan]

Jeg tager denne fejl efter at simulere denne kode: kan ikke finde en pinstub / havn i symbolet, funktionsprototype, eller andre opføre "prøve", som repræsenterer et design-fil, der svarer til pin XA2 i filen.

dette er en 16 bit CSA simulator

Tak for hjælp
Min

Koden er Herunder:

- 16 BIT CARRY SKIP ADDER ----
LIBRARY IEEE;
Brug ieee.std_logic_1164.all;

enhed CSA_FIXED_SIZE er
havn (X, Y: IN std_logic_vector (15 downto 0); - girisler
C: I STD_LOGIC - C girisi
S: OUT std_logic_vector (3 downto 0);
Retten: out STD_LOGIC) - C cikisi
ende CSA_FIXED_SIZE;arkitektur STRUKTUR AF CSA_FIXED_SIZE IS

Komponent adder5
havn (tempX, tempY: IN std_logic_vector (3 downto 0);
tempC: I STD_LOGIC;
temps: out std_logic_vector (3 downto 0);
tempCout: OUT STD_LOGIC);
ende komponent;

Komponent skip4
havn (SCin, SCP: I STD_LOGIC;
SP: IN std_logic_vector (3 downto 0);
Scout: OUT STD_LOGIC);
ende komponent;

- Signal signalP: std_logic_vector (15 downto 0);
- signal signalC: std_logic_vector (3 downto 0);
- signal skipCout: std_logic_vector (2 downto 0);begynd

Test: adder5 port map (X (3 downto 0), Y (3 downto 0), K, S (3 downto 0), Court);
- RCA1: adder5 port map (X (3 downto 0), Y (3 downto 0), C, signalP (3 downto 0), signalC (0));
- SKIP1: skip4 port map (C, signalC (0), signalP (3 downto 0), skipCout (0));
- RCA2: adder5 port map (X (7 downto 4), Y (7 downto 4), skipCout (0), signalP (7 downto 4), signalC (1));
- SKIP2: skip4 port map (skipCout (0), signalC (1), signalP (7 downto 4), skipCout (1));
- RCA3: adder5 port map (X (11 downto

<img src="http://www.edaboard.com/images/smiles/icon_cool.gif" alt="Kølig" border="0" />

, Y (11 downto

<img src="http://www.edaboard.com/images/smiles/icon_cool.gif" alt="Kølig" border="0" />

, skipCout (1), signalP (11 downto

<img src="http://www.edaboard.com/images/smiles/icon_cool.gif" alt="Kølig" border="0" />

, signalC (2));
- SKIP3: skip4 port map (skipCout (1), signalC (2), signalP (11 downto

<img src="http://www.edaboard.com/images/smiles/icon_cool.gif" alt="Kølig" border="0" />

, skipCout (2));
- RCA4: adder5 port map (X (15 downto 12), Y (15 downto 12), skipCout (2), signalP (15 downto 12), signalC (3));
- Ss: skip4 port map (skipCout (2), signalC (3), signalP (15 downto 12), Court) - skipOut (3)
SLUT STRUCTURAL;-------------------------------------------------- ------------------
-------------------------------------------------- --------------------

- 4 BIT RIPLE CARRY BLOCK ----
----------------------------
LIBRARY IEEE;
Brug ieee.std_logic_1164.all;

enhed adder5 er
havn (XA, YA: IN std_logic_vector (3 downto 0);
Cin: I STD_LOGIC;
SA: OUT std_logic_vector (3 downto 0);
Retten: OUT STD_LOGIC);
ende adder5;arkitektur struktur adder5 Is
signal C1, C2, C3: STD_LOGIC;
Komponent fulladd
havn (Cin1, x1, y1: I STD_LOGIC;
s1, Cout1: OUT STD_LOGIC);
ende komponent;
begynd
stage0: fulladd port map (Cin, XA (0), YA (0), SA (0), C1);
stage1: fulladd port map (c1, XA (1), YA (1), SA (1), c2);
stage2: fulladd port map (c2, XA (2), YA (2), SA (2), C3);
stage3: fulladd port map (Cin1 => C3, Cout1 => Domstolen, x1 => XA (3), y1 => YA (3), s1 => SA (3));

ende Struktur;

--- 1 BIT FULL ADDER BLOCK ----
LIBRARY IEEE;
Brug ieee.std_logic_1164.all;
enhed fulladd IS
havn (CIN2, x2, y2: I STD_LOGIC;
S2, Cout2: OUT STD_LOGIC);
ende fulladd;

ARKITEKTUR LogicFunc AF fulladd IS
begynd
s2 <= x2 XOR y2 XOR CIN2;
Cout2 <= (x2 og y2) eller (CIN2 og x2) eller (CIN2 og y2);
ende LogicFunc;

------------------------------------------
------------------------------------------

--- 4 BIT FULL SKIP BLOCK ----
LIBRARY IEEE;
BRUG IEEE.std_logic_1164.all;

ENTITY skip4 IS
havn (Cin, Cp: I STD_LOGIC;
P: IN std_logic_vector (3 downto 0);
Retten: OUT STD_LOGIC);
ende skip4;
ARKITEKTUR davranissal AF skip4 IS
BEGIN
Retten <= Cp eller (P (0) og P (1) og P (2) og P (3) og Cin);
SLUT davranissal;