qusetion på asynkron FIFO

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Hej alle

For nylig har jeg skrevet koden til asynkron FIFO.
Nedenfor er min kode:Kode:

modul asyn_FIFO (Data_out, FIFO_full, FIFO_empty, Data_in, write_clk, read_clk, write_to_FIFO, read_from_FIFO, reset);parameter FIFO_width = 8;

parameter FIFO_height = 8;

parameter FIFO_ptr_width = 3;output [FIFO_width-1: 0] Data_out;

output FIFO_full;

output FIFO_empty;input [FIFO_width-1: 0] Data_in;

input write_clk;

input read_clk;

input write_to_FIFO;

input read_from_FIFO;

input reset;reg [FIFO_ptr_width-1: 0] write_addr, read_addr;

reg [FIFO_width-1: 0] Data_out;

reg [FIFO_width-1: 0] FIFO [FIFO_height-1: 0];wire read_synch;

wire write_synch;

wire [FIFO_width-1: 0] Data_middle;integer i;tildele FIFO_full = ((write_addr == read_addr) & & (write_to_FIFO == 1));

tildele FIFO_empty = ((write_addr == read_addr) & & (read_from_FIFO == 1));altid @ (posedge write_clk eller posedge reset)

if (reset) begynder

write_addr <= 3'b000;

for (i = 0; i <= FIFO_height-1; i = i 1)

FIFO <= 8'b0000_0000;

ende

else if ((write_synch )&&(! FIFO_full)) begynder

FIFO [write_addr] <= Data_middle;

write_addr <= write_addr 1;

endealtid @ (posedge read_clk eller posedge reset)

if (reset) begynder

read_addr <= 3'b000;

Data_out <= 8'b0000_0000;

ende

ellers begynder

if ((read_synch )&&(! FIFO_empty)) begynder

Data_out <= FIFO [read_addr];

read_addr <= read_addr 1;

ende

endesynchronizer_write s1 (Data_middle, write_synch, write_clk, write_to_FIFO, reset, Data_in);

synchronizer_read s2 (read_synch, read_from_FIFO, read_clk, reset);endmodulemodul synchronizer_write (Data_out, write_synch, CLK, Data_valid, reset, Data_in);parameter Data_width = 8;output [Data_width-1: 0] Data_out;

output write_synch;input CLK;

input reset;

input Data_valid;

input [Data_width-1: 0] Data_in;reg Data_valid_synch;

reg write_synch;

reg [Data_width-1: 0] Data_out;altid @ (posedge CLK eller posedge reset)

if (reset) begynder

Data_valid_synch <= 0;

write_synch <= 0;

ende

ellers begynder

Data_valid_synch <= Data_valid;

write_synch <= Data_valid_synch;

endealtid @ (posedge CLK eller posedge reset)

if (reset)

Data_out <= 8'b0000_0000;

ellers begynder

if (write_synch)

Data_out <= Data_in;

endeendmodulemodul synchronizer_read (read_synch, read_from_FIFO, clk, reset);output read_synch;

input read_from_FIFO;

input CLK;

input reset;reg meta_synch, read_synch;altid @ (posedge CLK eller posedge reset)

if (reset) begynder

meta_synch <= 0;

read_synch <= 0;

ende

ellers begynder

meta_synch <= read_from_FIFO;

read_synch <= meta_synch;

endeendmodule

 

[weilijun]

Jeg er bange for, at du cann't tilføje "count <= count 1" under koden "write_addr <= write_addr 1" og "count <= count-1" under koden "read_addr <= read_addr-1".Hvis du gør det, vil konkurrencetilstand opstå og resultere i fejl.
Den almindelige måde at gennemføre en asynchorous FIFO er at bruge Gray kode for at skrive adresse og læse adresse.Så kan du sammenligne de to adresser at vide, om FIFO er fuld eller tom.