L
littlewing
Guest
I have some code that fails in the simulator but seemingly is OK when
synthesized:
entity synchronizer is
generic ( stages : positive:= 3);
port (
inval, clock: in std_logic;
outval : out std_logic
);
end entity;
architecture rtl of synchronizer is
signal shifter : std_logic_vector(0 to stages);
begin
shifter(0) <= inval; -- Assignment outside of process
process(clock)
begin
if rising_edge(clock) then
for i in 1 to stages loop
shifter(i) <= shifter(i-1); -- Assignment inside of process
end loop;
end if;
end process;
outval <= shifter(stages);
end architecture;
In the simulator (late-model Vivado default), the \"out\" signal drives to
\"X\" = illegal value, messing up my whole design.
I can fix it by moving the assignment to shifter(0) into the process and
changing the sensitivity list as follows: (only process shown)
process(clock, inval) -- \"inval\" included in sensitivity list
begin
shifter(0) <= inval; -- Assignment inside of process
if rising_edge(clock) then
for i in 1 to stages loop
shifter(i) <= shifter(i-1); -- Assignment inside of process
end loop;
end if;
end process;
Apparently the simulator thinks I am assigning two values to one
destination. I try to assign to part of \"shifter\" outside of the
process and the rest of it inside of the process. In VHDL, is the
array considered one signal, or is it a convenience to describe a
multiplicity of independent signals? Is my original code incorrect?
synthesized:
entity synchronizer is
generic ( stages : positive:= 3);
port (
inval, clock: in std_logic;
outval : out std_logic
);
end entity;
architecture rtl of synchronizer is
signal shifter : std_logic_vector(0 to stages);
begin
shifter(0) <= inval; -- Assignment outside of process
process(clock)
begin
if rising_edge(clock) then
for i in 1 to stages loop
shifter(i) <= shifter(i-1); -- Assignment inside of process
end loop;
end if;
end process;
outval <= shifter(stages);
end architecture;
In the simulator (late-model Vivado default), the \"out\" signal drives to
\"X\" = illegal value, messing up my whole design.
I can fix it by moving the assignment to shifter(0) into the process and
changing the sensitivity list as follows: (only process shown)
process(clock, inval) -- \"inval\" included in sensitivity list
begin
shifter(0) <= inval; -- Assignment inside of process
if rising_edge(clock) then
for i in 1 to stages loop
shifter(i) <= shifter(i-1); -- Assignment inside of process
end loop;
end if;
end process;
Apparently the simulator thinks I am assigning two values to one
destination. I try to assign to part of \"shifter\" outside of the
process and the rest of it inside of the process. In VHDL, is the
array considered one signal, or is it a convenience to describe a
multiplicity of independent signals? Is my original code incorrect?